sccb.c 7.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260
  1. /*
  2. * This file is part of the OpenMV project.
  3. * Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
  4. * This work is licensed under the MIT license, see the file LICENSE for details.
  5. *
  6. * SCCB (I2C like) driver.
  7. *
  8. */
  9. #include <stdbool.h>
  10. #include <freertos/FreeRTOS.h>
  11. #include <freertos/task.h>
  12. #include "sccb.h"
  13. #include <stdio.h>
  14. #include "sdkconfig.h"
  15. #if defined(ARDUINO_ARCH_ESP32) && defined(CONFIG_ARDUHAL_ESP_LOG)
  16. #include "esp32-hal-log.h"
  17. #else
  18. #include "esp_log.h"
  19. static const char* TAG = "sccb";
  20. #endif
  21. //#undef CONFIG_SCCB_HARDWARE_I2C
  22. #define LITTLETOBIG(x) ((x<<8)|(x>>8))
  23. #ifdef CONFIG_SCCB_HARDWARE_I2C
  24. #include "driver/i2c.h"
  25. #define SCCB_FREQ 100000 /*!< I2C master frequency*/
  26. #define WRITE_BIT I2C_MASTER_WRITE /*!< I2C master write */
  27. #define READ_BIT I2C_MASTER_READ /*!< I2C master read */
  28. #define ACK_CHECK_EN 0x1 /*!< I2C master will check ack from slave*/
  29. #define ACK_CHECK_DIS 0x0 /*!< I2C master will not check ack from slave */
  30. #define ACK_VAL 0x0 /*!< I2C ack value */
  31. #define NACK_VAL 0x1 /*!< I2C nack value */
  32. #if CONFIG_SCCB_HARDWARE_I2C_PORT1
  33. const int SCCB_I2C_PORT = 1;
  34. #else
  35. const int SCCB_I2C_PORT = 0;
  36. #endif
  37. static uint8_t ESP_SLAVE_ADDR = 0x3c;
  38. #else
  39. #include "twi.h"
  40. #endif
  41. int SCCB_Init(int pin_sda, int pin_scl)
  42. {
  43. ESP_LOGI(TAG, "pin_sda %d pin_scl %d\n", pin_sda, pin_scl);
  44. #ifdef CONFIG_SCCB_HARDWARE_I2C
  45. //log_i("SCCB_Init start");
  46. i2c_config_t conf;
  47. conf.mode = I2C_MODE_MASTER;
  48. conf.sda_io_num = pin_sda;
  49. conf.sda_pullup_en = GPIO_PULLUP_ENABLE;
  50. conf.scl_io_num = pin_scl;
  51. conf.scl_pullup_en = GPIO_PULLUP_ENABLE;
  52. conf.master.clk_speed = SCCB_FREQ;
  53. i2c_param_config(SCCB_I2C_PORT, &conf);
  54. i2c_driver_install(SCCB_I2C_PORT, conf.mode, 0, 0, 0);
  55. #else
  56. twi_init(pin_sda, pin_scl);
  57. #endif
  58. return 0;
  59. }
  60. uint8_t SCCB_Probe()
  61. {
  62. #ifdef CONFIG_SCCB_HARDWARE_I2C
  63. uint8_t slave_addr = 0x0;
  64. while(slave_addr < 0x7f) {
  65. i2c_cmd_handle_t cmd = i2c_cmd_link_create();
  66. i2c_master_start(cmd);
  67. i2c_master_write_byte(cmd, ( slave_addr << 1 ) | WRITE_BIT, ACK_CHECK_EN);
  68. i2c_master_stop(cmd);
  69. esp_err_t ret = i2c_master_cmd_begin(SCCB_I2C_PORT, cmd, 1000 / portTICK_RATE_MS);
  70. i2c_cmd_link_delete(cmd);
  71. if( ret == ESP_OK) {
  72. ESP_SLAVE_ADDR = slave_addr;
  73. return ESP_SLAVE_ADDR;
  74. }
  75. slave_addr++;
  76. }
  77. return ESP_SLAVE_ADDR;
  78. #else
  79. uint8_t reg = 0x00;
  80. uint8_t slv_addr = 0x00;
  81. ESP_LOGI(TAG, "SCCB_Probe start");
  82. for (uint8_t i = 0; i < 127; i++) {
  83. if (twi_writeTo(i, &reg, 1, true) == 0) {
  84. slv_addr = i;
  85. break;
  86. }
  87. if (i!=126) {
  88. vTaskDelay(10 / portTICK_PERIOD_MS); // Necessary for OV7725 camera (not for OV2640).
  89. }
  90. }
  91. return slv_addr;
  92. #endif
  93. }
  94. uint8_t SCCB_Read(uint8_t slv_addr, uint8_t reg)
  95. {
  96. #ifdef CONFIG_SCCB_HARDWARE_I2C
  97. uint8_t data=0;
  98. esp_err_t ret = ESP_FAIL;
  99. i2c_cmd_handle_t cmd = i2c_cmd_link_create();
  100. i2c_master_start(cmd);
  101. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | WRITE_BIT, ACK_CHECK_EN);
  102. i2c_master_write_byte(cmd, reg, ACK_CHECK_EN);
  103. i2c_master_stop(cmd);
  104. ret = i2c_master_cmd_begin(SCCB_I2C_PORT, cmd, 1000 / portTICK_RATE_MS);
  105. i2c_cmd_link_delete(cmd);
  106. if(ret != ESP_OK) return -1;
  107. cmd = i2c_cmd_link_create();
  108. i2c_master_start(cmd);
  109. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | READ_BIT, ACK_CHECK_EN);
  110. i2c_master_read_byte(cmd, &data, NACK_VAL);
  111. i2c_master_stop(cmd);
  112. ret = i2c_master_cmd_begin(SCCB_I2C_PORT, cmd, 1000 / portTICK_RATE_MS);
  113. i2c_cmd_link_delete(cmd);
  114. if(ret != ESP_OK) {
  115. ESP_LOGE(TAG, "SCCB_Read Failed addr:0x%02x, reg:0x%02x, data:0x%02x, ret:%d", slv_addr, reg, data, ret);
  116. }
  117. return data;
  118. #else
  119. uint8_t data=0;
  120. int rc = twi_writeTo(slv_addr, &reg, 1, true);
  121. if (rc != 0) {
  122. data = 0xff;
  123. } else {
  124. rc = twi_readFrom(slv_addr, &data, 1, true);
  125. if (rc != 0) {
  126. data=0xFF;
  127. }
  128. }
  129. if (rc != 0) {
  130. ESP_LOGE(TAG, "SCCB_Read [%02x] failed rc=%d\n", reg, rc);
  131. }
  132. return data;
  133. #endif
  134. }
  135. uint8_t SCCB_Write(uint8_t slv_addr, uint8_t reg, uint8_t data)
  136. {
  137. #ifdef CONFIG_SCCB_HARDWARE_I2C
  138. esp_err_t ret = ESP_FAIL;
  139. i2c_cmd_handle_t cmd = i2c_cmd_link_create();
  140. i2c_master_start(cmd);
  141. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | WRITE_BIT, ACK_CHECK_EN);
  142. i2c_master_write_byte(cmd, reg, ACK_CHECK_EN);
  143. i2c_master_write_byte(cmd, data, ACK_CHECK_EN);
  144. i2c_master_stop(cmd);
  145. ret = i2c_master_cmd_begin(SCCB_I2C_PORT, cmd, 1000 / portTICK_RATE_MS);
  146. i2c_cmd_link_delete(cmd);
  147. if(ret != ESP_OK) {
  148. ESP_LOGE(TAG, "SCCB_Write Failed addr:0x%02x, reg:0x%02x, data:0x%02x, ret:%d", slv_addr, reg, data, ret);
  149. }
  150. return ret == ESP_OK ? 0 : -1;
  151. #else
  152. uint8_t ret=0;
  153. uint8_t buf[] = {reg, data};
  154. if(twi_writeTo(slv_addr, buf, 2, true) != 0) {
  155. ret=0xFF;
  156. }
  157. if (ret != 0) {
  158. ESP_LOGE(TAG, "SCCB_Write [%02x]=%02x failed\n", reg, data);
  159. }
  160. return ret;
  161. #endif
  162. }
  163. uint8_t SCCB_Read16(uint8_t slv_addr, uint16_t reg)
  164. {
  165. #ifdef CONFIG_SCCB_HARDWARE_I2C
  166. uint8_t data=0;
  167. esp_err_t ret = ESP_FAIL;
  168. uint16_t reg_htons = LITTLETOBIG(reg);
  169. uint8_t *reg_u8 = (uint8_t *)&reg_htons;
  170. i2c_cmd_handle_t cmd = i2c_cmd_link_create();
  171. i2c_master_start(cmd);
  172. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | WRITE_BIT, ACK_CHECK_EN);
  173. i2c_master_write_byte(cmd, reg_u8[0], ACK_CHECK_EN);
  174. i2c_master_write_byte(cmd, reg_u8[1], ACK_CHECK_EN);
  175. i2c_master_stop(cmd);
  176. ret = i2c_master_cmd_begin(SCCB_I2C_PORT, cmd, 1000 / portTICK_RATE_MS);
  177. i2c_cmd_link_delete(cmd);
  178. if(ret != ESP_OK) return -1;
  179. cmd = i2c_cmd_link_create();
  180. i2c_master_start(cmd);
  181. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | READ_BIT, ACK_CHECK_EN);
  182. i2c_master_read_byte(cmd, &data, NACK_VAL);
  183. i2c_master_stop(cmd);
  184. ret = i2c_master_cmd_begin(SCCB_I2C_PORT, cmd, 1000 / portTICK_RATE_MS);
  185. i2c_cmd_link_delete(cmd);
  186. if(ret != ESP_OK) {
  187. ESP_LOGE(TAG, "W [%04x]=%02x fail\n", reg, data);
  188. }
  189. return data;
  190. #else
  191. uint8_t data=0;
  192. uint16_t reg_htons = LITTLETOBIG(reg);
  193. uint8_t *reg_u8 = (uint8_t *)&reg_htons;
  194. uint8_t buf[] = {reg_u8[0], reg_u8[1]};
  195. int rc = twi_writeTo(slv_addr, buf, 2, true);
  196. if (rc != 0) {
  197. data = 0xff;
  198. } else {
  199. rc = twi_readFrom(slv_addr, &data, 1, true);
  200. if (rc != 0) {
  201. data=0xFF;
  202. }
  203. }
  204. if (rc != 0) {
  205. ESP_LOGE(TAG, "R [%04x] fail rc=%d\n", reg, rc);
  206. }
  207. return data;
  208. #endif
  209. }
  210. uint8_t SCCB_Write16(uint8_t slv_addr, uint16_t reg, uint8_t data)
  211. {
  212. static uint16_t i = 0;
  213. #ifdef CONFIG_SCCB_HARDWARE_I2C
  214. esp_err_t ret = ESP_FAIL;
  215. uint16_t reg_htons = LITTLETOBIG(reg);
  216. uint8_t *reg_u8 = (uint8_t *)&reg_htons;
  217. i2c_cmd_handle_t cmd = i2c_cmd_link_create();
  218. i2c_master_start(cmd);
  219. i2c_master_write_byte(cmd, ( slv_addr << 1 ) | WRITE_BIT, ACK_CHECK_EN);
  220. i2c_master_write_byte(cmd, reg_u8[0], ACK_CHECK_EN);
  221. i2c_master_write_byte(cmd, reg_u8[1], ACK_CHECK_EN);
  222. i2c_master_write_byte(cmd, data, ACK_CHECK_EN);
  223. i2c_master_stop(cmd);
  224. ret = i2c_master_cmd_begin(SCCB_I2C_PORT, cmd, 1000 / portTICK_RATE_MS);
  225. i2c_cmd_link_delete(cmd);
  226. if(ret != ESP_OK) {
  227. ESP_LOGE(TAG, "W [%04x]=%02x %d fail\n", reg, data, i++);
  228. }
  229. return ret == ESP_OK ? 0 : -1;
  230. #else
  231. uint8_t ret=0;
  232. uint16_t reg_htons = LITTLETOBIG(reg);
  233. uint8_t *reg_u8 = (uint8_t *)&reg_htons;
  234. uint8_t buf[] = {reg_u8[0], reg_u8[1], data};
  235. if(twi_writeTo(slv_addr, buf, 3, true) != 0) {
  236. ret = 0xFF;
  237. }
  238. if (ret != 0) {
  239. ESP_LOGE(TAG, "W [%04x]=%02x %d fail\n", reg, data, i++);
  240. }
  241. return ret;
  242. #endif
  243. }